The Texas Instruments ADC34J2 series provides high linearity, ultra-low power, dual-channel, 12-bit, 50MSPS to 160MSPS analog-to-digital converters (ADC).
These devices are specifically designed to support high input frequency signals that require large dynamic range. The clock input divider provides greater flexibility for the design of the system clock architecture, while the SYSREF input achieves complete system synchronization.
The device supports the JESD204B interface to reduce the number of interface lines, thereby achieving high system integration. The JESD204B interface is a serial interface, and the data of each ADC is serialized and output through only one differential pair. The internal phase-locked loop (PLL) multiplies the input ADC sampling clock by 20 to obtain the bit clock used to serialize the 12-bit data of each channel. The device supports subclass 1 with interface speeds up to 3.2Gbps.
